عنوان مقاله
مسیریابی مهاجرت الکتریک-آگاه برای مدارهای مجتمع سه بعدی با نمونه سازی مهاجرت الکتریکی استرس-آگاه
فهرست مطالب
مقدمه
محرک
مدل سازیEM استرس-آگاه برای مدارهای مجتمع سه بعدی
مسیریابی EM- آگاه برای مدارهای مجتمع سه بعدی
نتیجه گیری
بخشی از مقاله
مدل سازی جریان مستقیم معادل برای شبکه های متناوب
بیشتر شبکه های سیگنال درVLSI شبکه های متناوب با جریان دو-مسیره هستند. در گذشته، شبکه های متناوب بعنوان شبکه های کم ارزش برایEM در نظر گرفته می شدند چون مسیر مخالف جریان بتواندEM را تا چندین درجه جبران کند. هرچند، اگر عدم تعادل جریان بین دو مسیر جریان وجود داشته باشد، EM نمیتواند کاملا لغو شود.
کلمات کلیدی:
Electromigration-aware Routing for 3D ICs with Stress-aware EM Modeling Jiwoo Pak Dept. of Electrical and Computer Engineering The Univ. of Texas at Austin jiwoo@cerc.utexas.edu Sung Kyu Lim School of Electrical and Computer Engineering Georgia Inst. of Tech. limsk@ece.gatech.edu David Z. Pan Dept. of Electrical and Computer Engineering The Univ. of Texas at Austin dpan@ece.utexas.edu Abstract—Electromigration (EM) has become a key reliability concern for nanometer IC designs. For 3D ICs, higher current density/temperature and TSV-induced thermal mechanical stress further exacerbate the EM issue compared to 2D ICs. In this paper, we analyze the root causes of EM for 3D IC signal nets, with consideration of current density, temperature, and TSV-induced thermal mechanical stress. We develop compact EM models for both DC and AC signal nets using detailed finite-element-analysis (FEA) and build EM library for meantime-to-failure (MTTF). For AC signal nets, we convert AC current into equivalent DC current and model EM with it. One unique property of EM in 3D ICs is that, depending on the current direction, TSV-induced stress may degrade or improve the MTTF, thus routing plays an important role for EM mitigation. We suggest EM-aware routing algorithms for 3D ICs for the first time to our best knowledge, guided by our stressaware EM modeling. Experimental result shows that our proposed approach improves EM-robustness of 3D IC benchmarks significantly, e.g., 66.4% less EM-violated grids with little sacrifice of conventional routing objectives. I. INTRODUCTION One of critical challenges for reliability of nano-scale VLSI is electromigration (EM) [1]. EM refers to the transport of material due to the movement of electrons, and this phenomenon is affected by various factors, such as geometrical shapes, temperature distribution, mechanical stress, current density, and material properties [2], [3]. EM on a wire accumulates more atoms at the end of the wire toward the source pin (anode) and creates hillocks while vacancies appear at the other end of the wire. As a result, circuits with more EM tend to become open or short circuits in a shorter time. EM causes more reliability issues with 3D IC technology. While 3D IC technology has beneficial features such as realization of small footprint, high bandwidth and suitability to heterogeneous systems, it also brings additional reliability issues such as mechanical stress from coefficient of thermal expansion (CTE) mismatch of TSV and silicon, higher temperature due to the stacked structure, and higher current density to drive multiple dies. These problems in 3D ICs are the factors that can aggravate the EM phenomenon even further. In traditional 2D ICs, a simple and effective way to reduce EM is decreasing current density. Hence, previous works to enhance EMrobustness focused on routing with optimization of wire width, or current-driven routing to achieve reliability [4]–[7]. Although these works provide reasonable ways to raise EM-robustness in 2D ICs, 3D ICs raise additional issues like mechanical stress and higher temperature on top of higher current density, thus wire width adjustment Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2012, November 5-8, 2012, San Jose, California, USA Copyright c 2012 ACM 978-1-4503-1573-9/12/11... $15.00 or current-driven routing are no longer sufficient to guarantee EMrobustness. For 3D ICs, new methodologies are needed to make EMaware routes, with consideration of TSV-induced mechanical stress and temperature, as well as current density. In this paper, we model EM with consideration of TSV-induced stress for signal nets, and propose a routing algorithm that increases EM-robustness in 3D ICs. Overall, our contributions are summarized as follows: • We efficiently analyze EM in 3D ICs with TSV-induced stress consideration, for both AC and DC signal nets • We effectively predict mean-time-to-failure (MTTF) at a certain location toward any routable direction, with given temperature, current density and TSV-induced stress gradient • We suggest a net ordering method based on EM-criticality and half-perimeter wire length (HPWL) • We propose EM-aware maze routing in 3D ICs using expected MTTF, for the first time to our best knowledge • We develop a technique to balance between EM-awareness and other routing constraints, to prevent over-sacrificing wire length while improving MTTF II. MOTIVATION Mechanical stress influences electromigration (EM); applied stress can either retard or accelerate EM depending on the stress gradient and the current direction [8]. We note that significant mechanical stress can be caused by TSVs after annealing process due to different CTE between copper and silicon [9]. Thus, TSV-induced stress can be a driving force for EM, and can affect EM of interconnects in 3D ICs [10]–[13]. We observe unique characteristics of EM in metal wires in 3D ICs from recent works in [12], [13]: 1) TSV-induced stress affects EM near TSV region 2) EM can be either mitigated or aggravated near TSV region depending on routing direction because stress gradient has an impact on EM, and the stress gradient varies with routing direction 3) The lowest metal layer (M1) can be the most dangerous layer on EM due to not only the highest current density and temperature, but also the highest stress gradient among all metal layers If TSV-induced stress had only negative effect on EM, avoiding TSV region could be the only solution in mitigating EM problem, and it could waste large routing resource. However, as EM-induced lifetime can be varied depending on the routing direction, EM-aware routing can further improve EM-robustness and utilize routing resource more effectively near TSV region. Moreover, since each metal layer has different TSV-induced stress, current density and temperature profiles, a smarter routing scheme can accommodate better reliability across multiple metal layers. In this work, we propose an EM-aware routing that can effectively choose EM-safe paths for multiple routing layers. To achieve the goal,
