عنوان مقاله
ATPG استرس-آگاه TSV برای مدارهای مجتمع پشته سازی شده
فهرست مطالب
چکیده
مقدمه
کارهای مربوطه
روش شناسی
نتیجه گیری
بخشی از مقاله
آزمایش مدارهای مجتمع سه بعدی
مدارهای مجتمع سه بعدی چالش های جدید برای مهندسان آزمایش معرفی میکند، که ممکن است شامل جاسازی های تست زیر باشد:
- تست قبل از اتصال انجام میشود تا قالب خوب شناخته شده قبل از پشته سازی را بدست آورد؛
- تست بعد از اتصال در طی پشته سازی و بعد از آن انجام میشود؛
- تست نهایی کل پشته و بسته را برای اطمینان از کیفیت محصول صادره را مد نظر دارد.
کلمات کلیدی:
TSV Stress-Aware ATPG for 3D Stacked ICs∗ Sergej Deutsch, Krishnendu Chakrabarty Department of Electrical and Computer Engineering Duke University Durham, NC 27708, USA {sergej.deutsch@duke.edu, krish@ee.duke.edu} Shreepad Panth, Sung Kyu Lim Department of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA 30332, USA {shreepad.panth@gatech.edu, limsk@ece.gatech.edu} Abstract—Thermo-mechanical stress due to TSV fabrication processes is a major concern in 3D integration. TSV stress not only degrades the mechanical reliability of 3D ICs but it also affects the electrical properties, such as electron and hole mobility, of the MOS devices surrounding TSVs. Variations in carrier mobility result in a change in the timing profile of the circuit, which has an impact on delay-fault testing. We show quantitatively using the SDQL metric that test quality is significantly reduced if the test patterns are generated with TSV stress-oblivious circuit models. We evaluate the impact on TSV stress on delay testing by considering layouts for several 3D logic-on-logic benchmarks. The test escape rate is higher for processes with lower yields. Our results also indicate that we can improve the test quality by using TSV-stress aware cell libraries in a conventional ATPG flow with commercial tools, with negligible impact on pattern count. We therefore conclude that any detrimental impact of TSV stress on pattern effectiveness and test quality can be overcome by using stress-aware models for test generation. I. INTRODUCTION Three-dimensional (3D) stacking with through-silicon-vias (TSVs) is a promising technology that can sustain Moore’s Law by providing high-bandwidth and high-speed interconnects between chips [1], [2]. TSVs are short metal pillars that go through the silicon substrate and connect the front side of one die with the back side of another die. Due to their small dimensions, TSVs offer a number of benefits over conventional stacking methods, such as higher interconnect density, higher performance, and lower power consumption. Figure 1 shows a generic 3D stack and Figure 2 shows a detailed layout of a circuit with TSVs. Despite the numerous benefits offered by 3D integration, test challenges for 3D ICs must be addressed before volume manufacturing and defect screening can be feasible [3], [4]. One of the serious problems confronting 3D integration is that of thermomechanical stress due to TSV processing. The thermal expansion coefficient of copper, a common TSV fill material, is significantly higher than that of silicon: 17×10−6/K versus 3×10−6/K [5]. Due to this mismatch, TSVs are likely to cause residual stress in the silicon during fabrication and thermal cycling. One of the effects of thermal stress is mobility variation in MOS devices in the proximity of TSVs. These variations lead to a change in the timing profile of the circuit [6], [7], which affects delay-fault testing. ∗The work of S. Deutsch and K. Chakrabarty was supported in part by the National Science Foundation under grant no. CCF-1017391 and by the Semiconductor Research Corporation (SRC) under contract no. 2118.001. The work of S. Panth and S. K. Lim was funded by Intel Corporation through SRC. Recent work on 3D IC testing has targeted solutions to overcome problems related to test access in 3D ICs and TSV testing. We focus here on post-bond delay-fault testing of internal die logic in 3D ICs, a problem that has received much less attention in the literature. We study the impact of timing variations due to TSV stress on the quality of test patterns generated to screen small-delay defects (SDDs). In particular, we focus on the following problems: (i) How severe is the impact of TSVinduced stress on the effectiveness of patterns for SDDs and test escapes? (ii) To what extent can test escapes be reduced by including analytical TSV stress models as a preprocessing step in the ATPG flow? (iii) What is the impact of TSV stress-aware ATPG on pattern count and how does the process yield affect test escapes due to TSV-induced stress? We assume that SDD testing is done after stacking, such that the clock tree for functional operation is available for at-speed capture cycles. We show that the use of TSV stress-oblivious circuit models results in a significantly increased escape rate of faulty chips. The level of this increase depends on the yield of the fabrication process; we conclude that accurate modeling of TSV stress is more important for processes with lower yields. The impact of TSV stress on pattern effectiveness is quantified using the statistical delay quality level (SDQL) metric [8]. This is a key metric in our approach, since the SDQL of a chip correlates with the expected test escape rate due to small-delay defects. We also show that the test escape can be reduced considerably by incorporating TSV stress in cell timing libraries and using these libraries with a commercial timing-aware ATPG tool. Therefore, any detrimental impact of TSV stress on pattern effectiveness and test quality can be overcome by using stress-aware models for test generation. We also show that TSV stress-aware testing leads to negligible increase, if any, in pattern count. The remainder of this paper is organized as follows. In Section II, we give an overview of related prior work, including 3D SIC testing, small-delay testing, and mobility variations due to TSV stress. Section III describes our methodology to create TSV stressaware test patterns using conventional ATPG tools. In Section IV, we present experimental results obtained with 3D logic-on-logic benchmarks. Finally, Section V concludes the paper. II. RELATED PRIOR WORK A. 3D IC Testing 3D ICs introduce new challenges for test engineers such as test access during the entire 3D test flow, which may include the
