عنوان مقاله
طراحی تقویت‌کننده قدرتAB کلاسCMOS باند-C برای تامین ولتاژ فوق‌العاده پایین 1.9V
فهرست مطالب
مقدمه
فرآیند طراحی
اندازه گیری نسبت به نتایج شبیه سازی
مقایسه حالت فنی
نتیجه گیری
بخشی از مقاله
تحلیل کشش بار
خروجی شبکه تطبیقی از اهمیت زیادی برخوردار است تا سطح قدرت مورد نظر را بدست آورد این نه تنها برای تطبیق امپدانس برای پایان خدمت، بلکه همچنین برای ارائه یک امپدانس بهینه برای ترانزیستور که منجر به حداکثر توان انتقال به بار می شود انجام می شود. برای اندازه ترانزیستور داده شده، بایاس و ورودی تطبیقی برآورده شده، نوسان امپدانس کشش بار دیده شده توسط ترانزیستور را تحلیل می‌کند و توان خروجی واقعی بدست آمده در سراسر بخش مقاومتی بار را محاسبه می‌کند.
کلمات کلیدی:
Design of a C-Band CMOS Class AB Power Amplifier for an Ultra Low Supply Voltage of 1.9 V Jörg Carls, Frank Ellinger, Ralf Eickhoff, Paulius Sakalas, Stefan von der Mark and Silvan Wehrli Dresden University of Technology, 01062 Dresden, Germany, Carls@iee.et.tu-dresden.de Abstract — Present day power amplifier (PA) design struggles with the fact that applicable supply voltages are continuously shrinking for short channel MOS transistors, which makes reaching high output power values increasingly difficult. This work develops a Class AB PA with an optimized load impedance for maximum output power with the help of a systematic loadpull analysis. It will display necessary trade offs for optimum output power and small signal gain. The presented PA, realized in CMOS, shows a measured output power of 19.8 dBm at 5.8 GHz for a supply voltage of 1.9 V. The drain efficiency at the 1 dB compression point reaches 28.1 %, the highest report up to today for this output power level. Index Terms — Power Amplifier, low supply voltage, load pull analysis. I. INTRODUCTION Power amplifiers for WLAN applications in the C band need to fulfill several crucial design specifications. Most important is a high output power value of typically around 20 dBm and higher. Furthermore, the architecture has to offer sufficient gain. Looking on the current climate debate, energy efficiency becomes increasingly important. Finally, the architecture should be producible with a low cost standard IC process in order to create a competitive product. While III/V semiconductor technologies can realize very high output power values together with comparably competitive efficiencies, they are still expensive in mass fabrication when compared to standard CMOS processes. MOSFETs, however, support only small supply voltages and therefore generally allow only small output power values for single amplifier stages. Furthermore, lower supply voltages simultaneously reduce the attainable efficiency levels. The ratio Vsat to VSupply increases, which reduces the achievable RF voltage swing in relation to the available supply voltage and thereby decreases the obtainable drain efficiency of the amplifier. State-of-theart power amplifiers are referenced by [1], [2] and [3]. One can clearly see the struggle between high output power and high efficiency. As output power decreases approximately quadratic for lowered supply voltages, one way to increase the output power is to use an output matching network that converts a small load impedance seen by the transistor into the 50 termination needed. This transforms a low RF voltage – and high RF current – swing at the transistor drain into a high RF voltage and moderate RF current swings at the load. The load pull analysis will screen the solution space of possible load impedance and helps choosing an optimum value with respect to output power level and small signal gain. The PA presented is intended for mobile wireless terminals working according to the 802.11.a and 802.11n standard. Low supply voltage and high efficiency is a must for reduced battery count and prolonged battery lifetime. The potential application areas are WLAN and local positioning services as developed in the Resolution Project [4]. II. DESIGN PROCESS A. Architecture Determination The Class AB PA introduced here uses a supply voltage of only 1.9 V and is intended for the frequency range between 5 and 6 GHz. The applied process is the IBM-7WL CMOS process with minimum gate lengths of 180 nm and a fT of up to 35 GHz for the MOS transistors The starting point of the design is the choice of the intended technology, architecture and operating point. The choice of MOSFETs, supporting 1.9 V, is based on the need for a cost competitive architecture that uses an ultra low supply voltage. The second selection is the chosen architecture and bias point. For output power levels of 20 dBm, a linearly amplifying PA biased in class AB with little distortion losses is a good choice for an one-stage PA design. The next step is to look at the transistor width. The goal of around 25 to 30 % drain efficiency signifies a DC current of around 200 mA. This in turn leads to a transistor width of 1 mm for a gate bias between 1.1 V and 1.2 V.
